The present embodiments relate to integrated circuits and, more particularly, to interface circuitry between a serial interface circuit and an array of processing elements in an integrated circuit.
Many modern applications in domains such as image and signal processing, particularly when coupled with real-time constraints, require the use of massively parallel computing architectures. These architectures often fulfill the demand for distributed memory and computing power, simple and regular communication structure, intensive use of pipelining, and local communication in time and space.
Massively parallel computing architectures are often implemented by an array of processing elements, which is sometimes also referred to as a processor array. A systolic array is often the preferred implementation form of such a processor array. A systolic array is a homogeneous network made out of relatively simple processors that are regularly and locally connected. Those processors are sometimes also referred to as processing elements or data processing units. Data circulate through these processors in a synchronous manner and interact where they meet.
An array of processing elements offers the possibility of optimizing power, time, and area, and can provide the I/O bandwidth which is necessary for the implementation of computational-intensive high-throughput algorithms. In many applications, the array of processing elements receives the data for processing through a serial interface circuit.